Wafer-Level Packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level, instead of packaging each individual unit after wafer dicing. WLP is essentially a chip-scale packaging (CSP) technology since the resulting package is practically the same size as the die. Furthermore, wafer-level packaging helps streamline the manufacturing process from wafer fabrication to customer shipment. It does this by allowing integration of wafer fabrication, packaging, test, and burn-in at wafer level.
Wafer-level packaging essentially includes extending the wafer fabrication processes to include device interconnection and device protection processes. One way of achieving this is by extending the conventional wafer fabrication process with an additional step that deposits a multi-layer thin-film metal rerouting and interconnection system to each device on the wafer. This is achieved using the same standard photolithography and thin film deposition techniques employed in the device fabrication itself.
This additional level of interconnection redistributes the peripheral bonding pads of each chip to an area array of underbump metal (UBM) pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these UBM pads.
For solid state imaging systems (e.g., CMOS/COD cameras), WLP generally tends to include a glass cover on the device. This provides the added benefits of securing the sensitive image sensor surface during the added manufacturing processes for the additional interconnects, under bump metalization, passivations, additional processes and solder bumping processes. Other benefits include providing a foreign material protection of the image sensor surface. Since the outside surface of the device is now some distance (the thickness of the glass and the bonding layer) away from the image sensor surface, the effects of added defects in subsequent processing and camera assembly can be reduced. The outer glass surface puts the defects out of the focal plane of the camera system.
Wafer level packed devices, and in particular, wafer level packed electro-optical devices implemented with an air-gap between a cover glass and silicon substrate, have rigidity and stress problems. It would be desirable to improve such devices.